1. Field of the Invention
The present invention relates to a thin film transistor (TFT) and a method for fabricating the same, and more particularly, to a coplanar TFT and a method for fabricating the same.
2. Discussion of the Related Art
Generally, a polysilicon TFT is used for a pixel electrode driving element and fundamental element of the peripheral circuit in a liquid crystal display (LCD). There are several kinds of TFTs, each having a different structure. A TFT structure depends on the position of its active layer and electrode. For example, in a staggered TFT, the gate electrode and source/drain electrodes are separated from each other with an active layer of semiconductor layer in between. On the other hand, in a coplanar TFT, the gate electrode and source/drain electrodes are formed on one side of an active layer of semiconductor layer.
FIGS. 1A to 1C are cross-sectional views showing a conventional method for fabricating a coplanar TFT using an oxide layer.
As shown in FIG. 1A, a semiconductor layer pattern 11 is formed on an insulating substrate 10, and polycrystallized by laser annealing to form a first polysilicon layer pattern 12A.
As shown in FIG. 1B, an oxide layer and polysilicon layer are sequentially formed on first polysilicon layer pattern 12A, and patterned to form an oxide layer 13 and second polysilicon layer pattern 12B. Then, impurities are ion-implanted into first and second polysilicon layer patterns 12A and 12B, to form a heavily doped semiconductor layer 15. Here, the upper portion of first polysilicon layer pattern 12A forms a heavily doped semiconductor layer 15, and the whole second polysilicon layer pattern 12B forms a heavily doped semiconductor layer 15.
As shown in FIG. 1C, an interlevel insulating layer 18 of either oxide or nitride is formed on the overall surface of the substrate, and selectively removed to form a contact hole exposing heavily doped semiconductor layer 15 disposed on first polysilicon layer pattern 12A. Then, source/drain electrodes 17 are formed in contact with heavily doped semiconductor layer 15 through the contact hole. Here, oxide layer 13 serves as a gate insulating layer, and heavily doped semiconductor layer 15 formed thereon serves as a gate electrode.
In the aforementioned conventional method, since the oxide layer, which is formed on the polysilicon layer pattern at a high temperature of more than 550.degree. C., is used for the gate insulating layer. Furthermore, the conventional method requires heat treatment at a high temperature of more than 600.degree. C. in order to reduce the resistance of the heavily doped semiconductor layer. These processes do not allow the use of glass substrate, such as a large Corning 7069.
FIGS. 2A and 2B are cross-sectional views showing another conventional method for fabricating a TFT.
As shown in FIG. 2A, a polysilicon pattern 12A is formed on an insulating substrate 10, and an oxide layer pattern 13 is formed at a temperature below 300.degree. C. using chemical vapor deposition (CVD) on a portion of polysilicon layer pattern 12A that will be a channel. Then, a heavily doped semiconductor layer 15 is formed on the upper portion of polysilicon layer pattern 12A formed on both sides of oxide layer pattern 13. Here, a heat treatment for forming the heavily doped semiconductor layer is carried out at a temperature below 300.degree. C.
As shown in FIG. 2B, an interlevel insulating layer 18, for example an oxide layer, is formed on the overall surface of the substrate at a high temperature of over 400.degree. C. and selectively removed to form a contact hole, thereby exposing a portion of heavily doped semiconductor layer 15. Then, source/drain electrodes 17 are formed in contact with heavily doped semiconductor layer 15 through the contact hole. Thereafter, a gate electrode 16 is formed of metal on a portion of interlevel insulating layer 18 placed on oxide layer pattern 13.